VLSI 2

VLSI

 

Pull up network (PIN)

  • transistors used to pull down (to achieve the required logic)

 

Pull down network (PDN)

  • transistors used to pull up (to achieve the required logic)

 

static power dissipation

  • when output is low current flows from high to ground

  • circuit does not pull all the way down to 0V

    • is determined by the ratio of resistance between the pull up and pull down

 

the source is the side with the lesser voltage, i.e.

  • n-type

    • conduct from Vd if

 

 

 

 

 

 

 

 

 

 

 

  • p-type

    • conduct from Vd if

 

Logic types

  • CMOS

  • NMOS

  • pseudo-CMOS

  • pseudo-NMOS

  • dynamic

 

Logical effort is for

  • a particular input

    • sometimes want a critical path to have a lower logical effort

 

PLAs

  • note that one does not do ANDs in the AND plane and ORs in the OR plane

    • but DO do something which creates the minterms for DNF

  • note that while

 

 

    gives the output ¬A+¬B, it's meaning when exiting the AND plane is ¬(¬A + ¬B), since the logic is a pull down

  • note the need to negate the output before it leaves the OR plane (for the same reason that it is a pull

    down, as in the previous point)+